Logic designs frequently use scan chains to enhance testability and test coverage. Typical scan chain implementations utilize four signals (Scan Data In, Scan Data Out, Scan Clock, and Scan Enable) connected to four pins. However, some small pin count packages do not have enough available pins even with a special test mode configuration.
Shown in FIG. 1 is a prior art general synchronous logic design implementation without the addition of a scan chain to facilitate testing. Pins A1, A2, and A3 are inputs, and pin A4 is an output. Pin SysClk provides the clock signal to node CLK of the flip/flops. Three flip/flops DTC0, DTC1, and DTC2 receive a common clock signal. They each receive one of the data input signals D1, D2, and D3 from the Combinational Logic circuit 20. The flip/flops DTC0, DTC1, and DTC2 have output signals Q1, Q2, and Q3 which are inputs to the Combinational Logic circuit 20. The Combinational Logic circuit 20 represents the combinational logic that generates the flip/flop inputs D1-D3 from the input signals A1-A3 and the flip/flop outputs Q1-Q3. The Combinational Logic circuit 20 also generates the output at pin A4 from input signals A1-A3 and the flip/flop outputs Q1-Q3. The number of input pins, the number of output pins, and the number of flip/flops can be significantly larger, but the circuit of FIG. 1 is sufficient to describe the operation of the device.
Shown in FIG. 2 is a prior art synchronous logic design implementation that includes a scan chain to facilitate testing by making the internal circuit nodes (the inputs and outputs of the combinational logic circuit) more controllable and more observable. This circuit is very similar to the circuit of FIG. 1 in that the Combinational Logic circuit 20 is the same and the circuit has the same number of flip/flops SDC0, SDC1, and SDC2. The flip/flops have been changed to scannable flip/flips which have an input selection multiplexer controlled by input node S to select between the normal mode input D (D1, D2, and D3) when the signal at node S is logic 0, and the scan mode input node SD when the signal at node S is logic 1. The signal at node S is determined by combining signal TestMode and signal ScanEnable at AND gate AND10. Multiplexer MUX10 is added to the circuit to select one of the input pins A3 (ScanClock) for the clock CLK to the flip/flops during the test mode of operation if the clock is not already from an external pin. Multiplexer MUX12 is added to select between the Q output Q3 of the last flip/flop SDC2 in the scan chain and the normal mode output Y4 (from the Combinational Logic 20 which could be the direct output of a flip/flop). And gate AND10 is added to ensure that the S inputs to the flip/flops are all set to logic 0 when the device is not in test mode of operation. This technique is called a scan chain because the flip/flops in the design are connected in a long chain to form a shift register in which data is input on a pin to the input of the first flip/flop. The output of the first flip/flop is connected to the input of the second flip/flop and so on until the output of the last flip/flop is connected to an output pin. This path allows the external testing circuitry to load the flip/flops in the design with any desired pattern by shifting in a set of data through the shift register. When the signal TestMode is logic 0, the logic performs it normal logic function. When the signal TestMode is logic 1, the logic circuit is configured for scan chain testing. During test mode, when the signal ScanEnable is set to logic 1 (node A1 in this example) the internal flip/flops are configured as a shift register with the input to the shift register from node A2 (ScanDataIn) and the output on node A4 (ScanDataOut). Pin A3 provides the clock (ScanClock) for the shift register. A complete set of data is shifted into the shift register (3 bits in this case). After this data is shifted in, the signal ScanEnable is set to logic 0 so that on the next active edge of signal ScanClock, the flip/flops latch data from the D inputs which come from the combinational logic circuit 20. Since the inputs to the combinational logic circuit 20 are able to be controlled by the data shifted into the flip/flops when signal ScanEnable=1, the inputs to the combinational logic circuit 20 are highly controllable. With signal ScanEnable=0, the flip/flops latch the output of the combinational logic circuit 20. By activating signal ScanClock only once while signal ScanEnable=0, the flip/flops will latch data from controlled inputs to the combinational logic circuit 20. By making signal ScanEnable=1, the data in the flip/flops can be shifted out on pin A4 (which can be simultaneous to shifting in the next set of input data). Monitoring the output data of the scan chain allows the data latched by the scan chain when signal ScanEnable=0 to be checked and this makes the design highly observable. This basic scan chain operation requires a minimum of 4 pins once the logic is enabled in test mode for signals ScanEnable, ScanDataIn, ScanDataOut, and ScanClock.